1. Field of the Invention
The present invention relates to an improvement of a semiconductor memory having a memory cell array capable of storing multi-level data having two or more bits in, e.g., one memory cell.
2. Description of the Related Art
In recent years, semiconductor memory technology has rapidly progressed, and storage capacity has been steadily increased at a rate of four times in three years. According to this, cost per bit is continuously decreased, to the point where the cost is lower than a magnetic disk device. In addition, since a semiconductor memory has no mechanically operated portion, the access speed of the memory device is higher than that of a magnetic disk device. Therefore, semiconductor memory is expected to update the hierarchy of memory devices. However, since a low-cost compact magnetic disk device has been developed, the cost per bit of a semiconductor memory is hard to make lower than that of a magnetic disk device yet.
In a semiconductor memory, it is difficult to rapidly decrease the cost per bit by an increase in storage capacity using micropatterning. Since a conventional memory cell can store only 1-bit data, an amount of data stored in a silicon chip is necessarily limited, and even a memory which has a maximum large capacity at present is a 16-Mbit memory.
When a semiconductor memory is used in place of a magnetic disk device, the function of a conventionally used random access memory (RAM) is not required, only a simple serial-access function is sufficient. In an operating system or application software intended for an existing magnetic disk device, 256 bits are regarded as one sector. Therefore, a function of serially outputting an amount of data corresponding to one sector is required for a semiconductor memory.
In a magnetic disk device, the following method of correcting bit errors is used. In this method, 20 to 30 check (redundancy) bits are added to one sector, and bit errors are corrected by an error detection/correction circuit. As an error correction code, the well-known BCH code or Reed-Solomon code is applied. For example, by using the Reed-Solomon code, when 48 check bits are added to 512 data bits, 5 bits can be detected, and 3 bits can be corrected. As other error correction methods, a byte error detection/correction method and a burst error detection/correction method are used.
When a semiconductor memory is used in place of a magnetic disk device, the above error detection/correction circuit must be accommodated in a chip, or an external circuit including the error detection/correction circuit must be arranged independently of the chip. In the former case, in addition to data bits, check bits must be arranged in the chip.
As described above, in order to obtain a low-cost semiconductor memory in which a maximum amount of data is stored in one chip, a multi-level storage method for storing data having two or more bits in one cell must be used. This multi-level storage method is described in, e.g., "An Experimental 2-bit/Cell Storage DRAM for Macrocell or Memory-on-Logic Application" IEEE Journal of Solid-State Circuits, Vol. 24, No. 2, April 1989, or "A 16-Level/Cell Dynamic Memory" 1985 IEEE Journal of Solid-State Circuits Conference p. 246,247.
However, in both the above multi-level storage methods, a control operation for a potential of a bit line or a word line is complicated. In addition, a data converter for converting multi-level data read from a memory cell into multi-bit data or converting multi-bit data into multi-level data to be written in a memory cell is required. This data converter has a complicated structure. When this data converter is used, it is difficult to access a plurality of memory cells at the same time. Therefore, a large amount of data cannot be easily accessed at a high speed.